Systems & Data Engineer • FPGA (SystemVerilog) • Low-Latency Systems
I build data systems that move and transform data efficiently, from production pipelines and APIs to low-level ingestion and memory paths. Production experience with SQL transformations, ETL/data pipelines, and API-driven systems; focused on reliability, performance, and system correctness. Also exploring low-level systems and FPGA-based data paths.
Open to consulting, technical architecture reviews, and focused systems/data engineering engagements.
Data systems, APIs, and SQL-driven DAG workflows.
Spatio-Temporal Database / Geospatial API
A data system that models curb regulations as a queryable API. Given inputs such as location, time range, vehicle type, and other parameters, it returns what actions are allowed.
(lat, lon, vehicle_type, ...) -> allowed curb actions
Encodes complex municipal rules into a unified query model for routing and compliance.
View Live System ↗Technical case study: Reducing OS overhead to improve ingestion throughput
Packet Formatter + AXI DMA Path
A SystemVerilog cut-through formatter on a Zynq-7000 that formats incoming AXI4-Stream packet data into fixed-width 32-byte records. Designed to feed AXI DMA into memory, producing structured records for downstream data processing in a cache-aligned SPSC ring buffer.
Cache-Aligned SPSC Ring Buffer
A pure C lock-free SPSC ring buffer designed to consume fixed-width records from a memory-mapped DMA buffer (planned integration). Prevents MESI-induced false sharing by padding atomic read/write indices to 64-byte L1 cache-line boundaries.
Throughput: ~18–28M msgs/sec (~3–5× faster than mutex queue)
View Benchmark Repo ↗Blog on first-principles and bridge-principles systems thinking, connecting human behavior, software, hardware, and meaning. I write about uncertainty, data semantics, systems design, and the hardware/software boundary.